1. Field of Invention
The present invention relates to a method for a non-volatile memory. More particularly, the present invention relates to a method for forming a flash reference memory cell. According to the invention, a floating well region for isolation between a floating gate and a substrate is formed on the substrate to prevent the problems of over-etching in a contact window process and misalignment in a floating gate process.
2. Description of Related Art
A non-volatile memory has currently been applicable to a variety of electronic devices for storing structural data, program data, and other repetitive access data. And among all programmable non-volatile memories, electrically erasable and programmable read only memory (EEPROM) is the one memory device widely adopted in personal computers (PC) and electronic equipment. A conventional EEPROM comprises a transistor with a floating gate and serves to perform write, erase, and data storage operations. But, such memory cell also suffers from a slow access speed. So, he recent developed EEPROM, such as flash memory has been designed to have a higher access speed.
The flash memory exhibits a more advanced performance in accessing data, than any other kind of nonvolatile memory, such as electrically erasable and programmable read only memories, for reading and writing (or programming). The merits of high-speed operation in flash memory have been regarded as very adaptable to portable computing apparatuses, cellular phones or digital still cameras. In general, there are several kinds of the flash memory, such as the NAND-type in which memory cells are connected from a bit line in parallel and the NOR-type in which memory cells are connected from a bit line in serial. It is well known that the NOR-type flash memory has a competitive speed for data accessing, which makes the NOR-type more advantageous than the NAND-type in a high-frequency memory system. In addition, there are also AND-type and DINOR-type flash memories.
Generally, a flash memory cell of a flash memory comprises two gates, one is a floating gate and the other is a control gate. Charges can be stored in the floating gate. The control gate governs the access of data. The floating gate is located under the control gate and in a xe2x80x9cfloatingxe2x80x9d state. A flash memory further comprises a flash memory cell array consisting of flash memory cells, a flash reference memory cell array consisting of flash reference memory cells, and a sense amplifier, in which the flash memory cell array and the flash reference memory cell array are similar in structure. The sense amplifier can receive a flash current from the flash memory cell and a reference current from the flash reference memory cell to judge the logical state of the flash memory cell, then, the sensed data is output.
FIG. 1 is a schematic, cross-sectional view showing the structure of a flash reference memory cell according to the prior art. As shown in FIG. 1, a tunneling oxide layer 102 is formed on a substrate 100, a floating gate 104 is formed on the tunneling oxide layer 102, and a dielectric layer 106 is formed on the floating gate 104. The gate structure of the flash reference memory cell comprises the tunneling oxide layer 102, the floating gate 104, and the dielectric layer 106.
FIG. 2 is a schematic, cross-sectional view showing an over-etching occurring in a flash reference memory cell of FIG. 1 when a contact window is formed.
As shown in FIG. 2, when the contact window 108 is over-etched, the contact window 108 would directly connect to the substrate 100, causing a process failure.
In addition, while forming the floating gate 104, the doping amount thereof is not too high. However, if the doping amount is too low, the floating gate can cause depletion. As a result, the effective thickness of the oxide layer between the floating gate 104 and the substrate 100 is increased, and the driving current of the flash memory cell is reduced. In other words, the resistance between the floating gate 104 and the contact window 108 is increased in the flash reference memory cell, and the RC delay is increased. Thus, the operation speed of the device is affected.
The present invention provides a method for forming a flash reference memory cell. The invention comprises the following steps. A floating well region is formed in a semiconductor substrate. A first dielectric layer is formed to cover the substrate. A defined floating gate is formed on the first dielectric layer and is aligned to the floating well. A second dielectric layer is formed on the substrate. A contact window is formed by defining the second dielectric layer to expose portions of the floating gate. A implantation process is conducted to implant ions into the exposed floating gate. A third dielectric layer is formed to cover the substrate and fills the contact window.
According to the invention, the well region in the substrate is used as the isolation between the floating gate and the substrate to prevent the problems of over-etching in the contact window process and misalignment in the floating gate process. The ion implantation process increases the amount of the dopant in the floating gate to reduce the resistance of the floating gate window, and to improve the RC delay of the flash reference cell. In addition, the floating gates in a flash memory cell array can be formed by a light doping process to prevent the RC delay of the floating gate in the flash reference memory cell from being affected and further to enhance the operation speed of the device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation oft he invention as claimed.